1. Field of the Invention
The present invention relates to a complementary metal oxide semiconductor (CMOS) input buffer circuit for converting an input signal lower than CMOS level into a CMOS level output signal, and more particularly, to a CMOS input buffer circuit, which is required to operate over a wide power supply voltage range and with lower current consumption.
2. Description of the Related Art
A CMOS input buffer circuit is a CMOS circuit capable of converting a voltage to be input to an input terminal of the CMOS circuit into a CMOS level signal corresponding to a power supply voltage for operating the CMOS circuit and outputting the CMOS level signal by judging whether an input level of the input voltage is High or Low, even if the input voltage has an indefinite level.
FIG. 7 illustrates a conventional CMOS input buffer circuit. A PMOS transistor 701 has a source connected to a power supply terminal VDD, a drain connected to an output terminal 720, and a gate connected to a drain of a PMOS transistor 702 and a drain of an NMOS transistor 704. The PMOS transistor 702 has a source connected to the power supply terminal VDD, and a gate connected to the output terminal 720. An NMOS transistor 703 has a source connected to a reference terminal GND, a drain connected to the output terminal 720, and a gate connected to an input terminal 710. The NMOS transistor 704 has a source connected to the reference terminal GND, and a gate connected to a drain of a PMOS transistor 706 and a drain of an NMOS transistor 707. An NMOS transistor 705 has a source connected to a source of the PMOS transistor 706, and a drain and a gate that are connected to the power supply terminal VDD. The PMOS transistor 706 has a gate connected to the input terminal 710. The NMOS transistor 707 has a source connected to the reference terminal GND, and a gate connected to the input terminal 710. Although not illustrated, the power supply terminal VDD is supplied with a High voltage of 3 V from a power source, while the reference terminal GND is supplied with a Low voltage of 0 V from the power source.
Subsequently, an operation of the conventional CMOS input buffer circuit is described. In this CMOS input buffer circuit, the PMOS transistors each have a threshold voltage of −0.5 V while the NMOS transistors each have a threshold voltage of 0.5 V.
First, if a Low voltage of 0 V is input to the input terminal 710, the NMOS transistor 703 and the NMOS transistor 707 are turned OFF while the PMOS transistor 706 is turned ON. The gate of the NMOS transistor 704 is supplied with 2.5 V, which is a voltage determined by subtracting the threshold voltage of the NMOS transistor 705 from 3 V. Accordingly, the NMOS transistor 704 is turned ON. Then, the gate of the PMOS transistor 701 becomes 0 V to turn ON the PMOS transistor 701. Consequently, the output terminal 720 outputs 3 V. The PMOS transistor 702 is turned OFF because the gate of the PMOS transistor 702 is 3 V. That is, if 0 V is input to the input terminal 710, the output terminal 720 outputs 3 V, which is a High voltage in terms of CMOS level. On the other hand, if 3 V is input to the input terminal 710, the output terminal 720 outputs 0 V, which is a Low voltage in terms of CMOS level.
In those cases, one MOS transistor is always turned OFF in each of three current paths, and hence the CMOS input buffer circuit consumes no current.
Next, if a voltage lower than CMOS level and equal to or higher than such a voltage as to allow the NMOS transistors to be turned ON is input to the input terminal 710, the NMOS transistor 703 is turned ON and accordingly the output terminal 720 becomes 0 V. Because the output terminal 720 is 0 V, the PMOS transistor 702 is turned ON. The NMOS transistor 707 is turned ON, and hence the gate of the NMOS transistor 704 becomes 0 V to turn OFF the NMOS transistor 704. Then, the gate of the PMOS transistor 701 becomes 3 V to turn OFF the PMOS transistor 701. That is, if a voltage lower than CMOS level and equal to or higher than such a voltage as to allow the NMOS transistors to be turned ON is input to the input terminal 710, the output terminal 720 outputs 0 V, which is a Low voltage in terms of CMOS level. However, because the source of the PMOS transistor 706 is 2.5 V, which is determined by subtracting the threshold voltage of 0.5 V of the NMOS transistor 705 from the voltage of 3 V of the power supply terminal VDD, the PMOS transistor 706 cannot be turned OFF until the gate of the PMOS transistor 706 is supplied with a voltage of 2 V or higher. Consequently, a current flows via the PMOS transistor 706 and the NMOS transistor 707, resulting in current consumption.
In this case, in order to prevent current consumption with an even lower input voltage, the source voltage of the PMOS transistor 706 needs to be lowered by, for example, a configuration in which two NMOS transistors 705 are connected in series (see, for example, Japanese Patent Application Laid-open No. 2000-13214 (FIG. 3)).
However, the conventional CMOS input buffer circuit has a minimum operating voltage that is defined by higher one of a total voltage of the threshold voltage of the NMOS transistor 705 and the threshold voltage of the NMOS transistor 704 and a total voltage of the threshold voltage of the NMOS transistor 705 and an absolute value of the threshold voltage of the PMOS transistor 706. For that reason, setting the source voltage of the PMOS transistor 706 to be low for the purpose of preventing current consumption poses a problem that a high minimum operating voltage is required.
Meanwhile, there has been devised a method in which a reference voltage circuit for outputting a reference voltage is added to the configuration of FIG. 7 such that an output of the reference voltage circuit is connected to the gate of the NMOS transistor 705. This configuration may eliminate a fear of the PMOS transistor 706 being turned ON when a voltage lower than CMOS level is input with a high power supply voltage. However, there is another problem that the added reference voltage circuit consumes a current.